This invention relates to the improvements of an information processing system including a high-performance input/output controller.
There are many known information processing systems each of which includes input/output devices and a host computer for controlling the operation of the input/output devices. The central processing unit (CPU) of this type of information processing system, generally uses several interrupt levels (interrupt priorities). One interrupt level was used for one input/output device. An example of this system is described in The Information Processing Handbook, published by the information processing academy of Japan.
However, high-performance, multi-operation input/output control devices have come to use several interrupt levels for one input/output control device. The information processing system whose control device has different interrupt levels, is also disclosed in the above publication. When one input/output control device outputs many interrupt priorities of different levels to an external CPU, many signal lines must be used, each for one interrupt priority. For this reason, the conventional information processing system has the fault of using many connections between the input/output device and CPU. Especially when the input/output control device is used in a large scale integrated circuit (LSI), there is the problem of the increase in the number of pins of the LSI chip, and the increased size of the chip. The increase of the number of pins and the size of the chip are undesirable from an economical point of view.
Further, it is sometimes necessary to change the interrupt level of high performance input/output control devices. In earlier systems, the interrupt level was determined by the relationship of the connections between the input/output control device and the CPU. For this reason, level changes in the systems were difficult.